This transceiver took three
years to design and build; 1990-92.
It has dual VFOs, dual-receive, digital read-out, IF shift, RIT,
RF speech clipping and filtering, panel-adjustable CW offset, a
250 Hz CW filter, a sensitive integrating squelch for 6 meter
DX, a no-pop, no-click AGC circuit, a non-crunching
noise blanker, and QSK with no dit shortening, no lag,
and 50 wpm break-in ability. It uses 142
transistors, 189 integrated circuits, 236 diodes and one 200
watt tube. No microprocessor, no synthesizer, and no phase-lock loops;
no phase noise, no spurs, and no birdies.
This photo shows only the main 40 MHz tunable IF section; the three
front-ends, for HF, 6M, and 2M, are on separate rack panels.